Short channel (below about 2 micron) insulated gate field effect transistors, also known as metal oxide semiconductor field effect transistors (MOSFETs), are desirable for high frequency operation, typically above 50 MHz. In the pending patent applications entitled "Method for Making Short Channel Transistor Devices," Ser. No. 141,121, filed by H. J. Levinstein on Apr. 17, 1980, and "Short Channel Field Effect Transistors," Ser. No. 141,120 filed by M. P. Lepselter et al. also on Apr. 17, 1980, now U.S. Pat. No. 4,343,082, methods are described for making insulated gate field effect transistors with extremely small (500 .ANG. or less) separations between the extremities of the gate regions and those of the source (and drain) regions. The transistors were therefore characterized by desirably small source-to-channel resistances.
The methods taught in the aforementioned Levinstein and Lepselter et al. patent applications include the formation of thin silicon dioxide layers on the sidewalls of polycrystalline silicon gate electrodes by thermal growth. The resulting sidewall oxide layer is useful as a spacer layer for aligning the source relative to the gate region channel.
Although rather thin (as low as about 200 .ANG.) layers of the required sidewall oxide can be formed by thermal growth of silicon dioxide on the polycrystalline silicon ("polysilicon") gate, an undesirable limitation of such thermal growth stems from the facts that: (1) oxide growth on the polysilicon is not easily controlled or uniform, owing to the polycrystalline structure of the underlying polysilicon; (2) at the same time that the sidewall oxide is being grown, the source-to-drain length of the polysilicon gate electrode correspondingly is diminished; so that control over the crucial length of the gate electrode, and hence of the underlying transistor channel, is deteriorated; (3) the oxides simultaneously grown over the source and drain regions force down the top surfaces of the source and drain to levels below the top surface of the channel region by undesirably large amounts (approximately equal to one-half the thickness of the grown oxide); and (4) a separate etching step is required for the removal of the grown oxide from locations overlying the source and drain.
Accordingly, it would be desirable to have a method for defining features in semiconductor transistor structures by forming sidewall oxide layers which mitigates one or more of these shortcomings of the prior art.